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November 2009 |
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• AONews: Mission Critical Newsflash • |
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November 2009 |
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• AONews: Mission Critical Newsflash • |
| Technology Insight |
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"Six Design & Development Considerations for Embedded Multi-Processor Systems" Over the past two years, Aonix has learned quite a lot about Symmetrical Multi-Processing (SMP) while bringing PERC Ultra SMP to market. Our experiences porting the PERC run-time, including real-time garbage collection, to SMP environments has reinforced the importance of balance in the design of software for multiprocessor architectures. Designers must strike a balance between dividing large tasks into many independent work activities that can be assigned to individual processors and minimizing the amount of coordination required between processors in receiving and carrying out independent work assignments. In our experience assisting several customers with the migration from single-processor to multi-processor Java, we have found that most customers also need to reconsider certain application software architecture tradeoffs in order to exploit the most benefit from the increased capacity of multiprocessor computers. The language used
can have an impact on multi-core application success. For instance,
unlike C and C++, Java provides a strong foundation for building
efficient, portable, and scalable applications and software
components that fully exploit whatever multiprocessing capabilities
are provided by the underlying hardware. Built into the
Java language is syntax to support multi-threading and robust
sharing of information
between threads. The Java memory model, unlike C and C++, makes
very clear when information updated by one thread will be reliably
propagated to other threads. Evidence from applications upgraded from single to multi-core functionality confirms that the performance gain is often less than expected, mainly due to basic misunderstandings of design considerations for the migration. To help developers get a better handle on what to expect, we wrote a white paper, "Six design & development considerations for embedded multi-processors systems". If you are planning to build or redeploy your application for multi-core execution, we hope this will help guide you toward successful deployment of your multi-core embedded system. |
Author
Established over 40 years ago, Moore’s law explains that processor capacity roughly doubles every two years. The doubling of capacity can be seen as doubling of memory sizes and processing speeds. In recent years, chip companies have found that the most effective way to profit from today’s wealth of transistors is to place multiple processing cores on the same chip. This paper discusses some of the issues associated with targeting symmetric multi-processor (SMP) platforms for embedded and real-time software systems. Most modern multi-core chips are structured as SMP systems, with very efficient (on-chip) communication between processors.
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